Parallel Viterbi decoding by breaking the compare-select feedback bottleneck

A solution is presented for implementing the add-compare-select (ACS) unit of a Viterbi decoder by parallel hardware for high data rates. For a fixed processing speed of the given hardware it allows a linear increase in throughput rate by a linear increase in hardware complexity. Thus arbitrary throughput rates can be achieved by linearly adding more parallel hardware elements. A systolic-array implementation of this parallel ACS unit of a Viterbi decoder is presented.<>