Reconfigurable particle filter design using dataflow structure translation

This paper presents reconfigurable particle filter design, which provides a capability of selecting a single particle filter from multiple particle filter realizations. The execution of the design is based on block level pipelining where data transfer between processing blocks is effectively controlled by autonomous controllers. With a simple switching mechanism that allows transformation of dataflow structure in addition to autonomous buffer controller, any desired particle filter can be performed. Two target particle filters, based on SIRF and GPF, are realized. From the execution characteristics obtained from the FPGA implementation, overall controller structure is derived according to the methodology and verified using Verilog and SystemC.