A high density, low leakage, 5T SRAM for embedded caches

This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV