Design of a lifting wavelet processor for one dimensional signal

This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using hardware description language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.