Auto-zero stabilized CMOS amplifiers for very low voltage or current offset

In this paper, we present two amplifiers designed in CMOS technology and including an auto-zero architecture for very low offset control. The first design is a high precision operational amplifier focusing on the voltage offset. It is a continuous time auto-zero stabilized architecture, that leads to a typical input offset voltage of 2 /spl mu/V-100nV//spl deg/C. The amplifier with its output buffer consumes 5mW at a supply voltage of +/- 2.5V. The gain bandwidth product is 2MHz while the slew rate is respectively -6V/ /spl mu/s and +8.8V/ /spl mu/s on 10pF with 10K/spl Omega/ load. This amplifier is suitable for the control of large dynamic (>10/sup 5/) calibration signal, and for very low DC signal instrumentation. The second design is a current mode charge pulse amplifier based on a second generation positive current conveyor topology (CCII). The bandwidth, the dynamic range and the output impedance have been optimized using an enhanced cascode current mirror. The preamplifier provides two outputs: one for the signal integration, and another going through a current comparator for a digital counting flow. The double hit resolution is less than Ins. An auto-zero compensation has been added to this preamplifier to control its output current offset down to 60nA. The total power dissipation (preamplifier + offset cancelation + comparator) is less than 1mW. This second amplifier has been designed for low power space applications, especially EUSO (Extreme Universe Space Observatory), which use multianode PMT in the configuration of a large gate time (2.5 /spl mu/s) open for charge integration.