An advanced library format for ASIC design

The design of an application specific integrated circuit (ASIC) relies on predefined components called cells. ASIC vendors use proprietary formals to describe technology cells and macro modules in conjunction with numerous translators to feed technology library data to electronic design automation (EDA) tools. Multiple formats are used to represent various aspects of the cells in the same technology library, such as behavior for simulation, timing parameters for synthesis, physical data for layout, noise parameters for signal integrity checks, etc. In addition, most of these are highly-tool oriented mere formats, and are not well-designed self-consistent grammars, and are hard to extend for new data models. In this paper we briefly discuss a library grammar that attempts to bridge the growing gap between new design rules and analysis required for high performance and complex design implementation, and accurate comprehensive modeling of library cells. Its modeling capability is equally applicable for large IP blocks and macro cells, thereby making it suitable for SoC designs as well.