A dual-band IEEE 802.11a/b/g receiver front-end using half-IF and dual-conversion

This paper presents a dual-band receiver front-end architecture which combines the dual-conversion and half-IF techniques for IEEE 802.1la/b/g. The proposed architecture receives dual-band signal with single receiver chain to reduce components count such as the 2/sup nd/ down-conversion mixer and VCO. The required LO frequencies of the dual-band application can be synthesized by only one VCO in combination with a divide-by-four circuit. An LC tank aided mechanism of mixer is also proposed to deal with the flicker noise. The core portion of the front-end receiver has been fabricated in 1P6M 0.18 /spl mu/m CMOS technology. The delivered gain, noise figure, and IIP3 are 20 dB, 3.5 dB, and -13 dBm, respectively simulated. The chip occupies an area of 1.21 /spl times/ 1.46mm/sup 2/ and the power consumption is 24mW under the supply voltage of 1.8V.