Packaging technology for imager using through-hole interconnections in Si substrate

For high-density packaging of ICs or other devices, it is one of the essential technologies to form through-hole interconnections in a Si substrate that electric circuits are built on in advance. We have developed a fabrication technology of wafer-level-packaging (WLP) for imagers, using the through-hole interconnections from the backside of the Si substrate to the top. The package consists of a glass cap protecting an image sensing area on the top side, the through-hole interconnections as leads, the copper re-routing and solder bumps on the backside. All processes of the packaging were done at wafer level. This paper describes the fabrication process and evaluation results of the mechanical and electrical characteristics of the WLP for imagers.