Performance analysis of clustered processors

Modern processors aim to achieve ILP by utilizing numerous functional units, large on-chip structures and wider issue windows. This leads to extremely complex designs, which in turn adversely affect clock rate. Hence, clustered processors have been introduced as an alternative, which allow high levels of ILP while maintaining a desirable clock rate. Nonetheless, clustering has its drawbacks. In this paper we discuss the two types of clustering-induced delays caused by limited intra-cluster issue bandwidth and inter-cluster communication latencies. We use simulation results to show that the stalls caused by inter-cluster communication delays are the dominant factor impeding the performance of clustered processors. We also use a set of models to illustrate how much performance could be improved if each type of delay was eliminated. Finally we show that as the issue width grows, or the number of clusters increases, effects of inter-cluster communication delays intensify severely while stalls caused by limited issue width remain insignificant in comparison. Our findings show that further improving the performance of current clustered processors may not be possible unless more advanced cluster assignment techniques are developed that minimize communication across clusters.