A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application

A technique for reducing the phase error of DLL/PLLs, due to non-ideal characteristics of the charge pump, is proposed. It makes the output of the charge pump virtually grounded, to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with a speed of 1.4 Gb/s.