An architecture for fractal image compression using quad-tree multiresolution

Nowadays the fractal image compression is realized by several methods, which are mainly focused to reduce the required number of operations. The present work describes a new architecture to realize fractal image compression. The architecture was designed to be used with a method based on a block classification scheme, using a quad-tree partition on multiple levels of resolution. The simplicity and regularity of the architecture and the method make them adequate to be implemented in programmable logical devices such as FPGAs, or in custom integrated VLSI circuits.