A high speed ASIC implementation of the Rijndael algorithm

In this study, a non-pipelined implementation of the Rijndael Algorithm, which is selected to be the new Advanced Encryption Algorithm (AES) by the National Institute of Standards and Technology (NIST) in October 2000, is presented. Both the encryption and the decryption algorithms of Rijndael are implemented on a single ASIC. Using 149 K gates in a 0.35-/spl mu/m standard CMOS process, we have reached a 132 MHz worst-case clock speed yielding 2.41 Gbit/s non-pipelined throughput in both encryption and decryption.