A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit

A novel fast true single phase clocking (TSPC) adiabatic differential logic circuit using dynamic threshold (DTMOS) is proposed (DT-TSPC-A). It is capable of operating at 0.7 V. The performance of four circuit architectures (DT-TSPC-A, conventional static CMOS logic, and two other published adiabatic circuits) is compared using a four inverter chain as the test circuit. At 50 MHz and 0.8 V with 20 fF load, this circuit consumes the least amount of energy of the four circuit architectures compared. It takes about the same area and consumes 55% less energy than the static circuit. It has the shortest delay and is 56% faster than other adiabatic circuits and takes at most 2.3 times the area. In addition results for more complex circuits are supplied demonstrating the improved performance of DT-TSPC-A circuits.