A power and area efficient multi-mode FEC processor

Forward Error Correction (FEC) is a key component in communication system which mostly contains scrambler, Reed-Solomon coding, interleaving, and trellis coding. For the performance and complexity issues, design parameters are different in various applications. In this paper, a multi-mode FEC processor is presented to meet different system requirements with a power and area efficient architecture. The proposed processor is fully compliant to ITU-T J.83 cable modem system including the reconfigurable Reed-Solomon decoder and memory-based universal convolutional interleaver. With 0.18 /spl mu/m 1P6M CMOS technology, the simulation result shows the FEC decoder can work over 100 MHz while costs 54.5 K gate counts and two 376/spl times/8 bits embedded duel-port SRAM. The average power consumption in most critical mode is about 34.2 mW at 100 MHz. While running at 7 MHz that meets symbol rate of cable modem, the power dissipation is 2.32 mW.