MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller

This paper proposes scalable H.264 video decoder architecture that makes the best use of memory bandwidth, which is the most critical problem during designing real-time multimedia CODEC, and optimizes memory access pattern. The proposed decoder architecture is based on an AHB AMBA system, which uses an ARM core as the main controller, and consists of functional blocks such as: VLD, IDCT, INTER (INTRA) prediction, DF, and Postprocessor. Especially, in order to meet memory bandwidth requirements for each functional block, reference frame memory structure, dual memory controller, and dual bus have been implemented, and the rationale for such design choices has been verified. The H.264 decoder proposed in this paper supports from baseline profile to 1080 HD under 130 MHz.