A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time

A 5.1-GHz integer-N CMOS phase locked loop (PLL) based frequency synthesizer is presented. A current mirror current source is used in designing the charge pump loop filter. A completely ripple-free VCO input control voltage is achieved using new mirror architecture in the charge pump loop filter. The acquisition time is improved by a factor of 1.62 using a new design methodology. The synthesizer operates from 4.92 to 5.1-GHz and achieves a phase noise of -121.9 dBc/Hz at 10-MHz offset frequency from the carrier for maximum oscillation frequency. The output rms jitter is 0.3% of the oscillator period. The total power consumption of this synthesizer is 10-mW. The PLL is designed and extracted in TSMC 0.18-/spl mu/m technology for GSM applications.