Design of a pixel array circuit for thinning process

In this paper, a pixel array circuit for image acquisition and thinning is presented. The circuit is designed to have a simple structure with four connections per pixel. In each pixel, the operations for the thinning process are performed using simple MOS switches and latches. Logic functions are implemented in NMOS pass transistor logic gates to minimize the circuit area and the power dissipation. The pixel array circuit can be implemented using a CMOS digital technology with a reasonable pixel density, which facilitates its integration in digital processing systems.