An improved frequency compensation techinique for low power, low voltage CMOS amplifiers [techinique read technique]

This paper presents an improved frequency compensation technique for low power and low voltage CMOS operational amplifier. The op amp designed for a high speed high resolution pipeline ADC is a two-stage with folded-cascode as the first stage and uses this improved compensation technique to achieve closed loop bandwidth of 350 MHz while driving a 2K resistor load and a 3.5 pF capacitive load consuming much lower power when compared to the conventional Miller compensation technique or cascode compensation technique. The op amp was designed in a 0.15-/spl mu/m CMOS technology and achieves a THD of 70 dB for a 30 MHz signal and consumes a total power of 4 mW of a 1.35 V supply.