A 0.35/spl mu/m CMOS 17-bit@40kS/s sensor A/D interface based on a programmable-gain cascade 2-1 /spl Sigma//spl Delta/ modulator

This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35/spl mu/m standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) /spl Sigma//spl Delta/ modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage op amps, has a fixed gain of 10 and it is capable of handling signals with 20KHz-bandwidth and amplitudes ranging from /spl mu/Vs to hundreds of mVs with a signal-to-(noise + distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulations results show 17-bit@40kS/s for all cases of the modulator gain.