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A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os | IEEE Journals & Magazine | IEEE Xplore

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os


Abstract:

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is ...Show More

Abstract:

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 39, Issue: 9, September 2004)
Page(s): 1553 - 1561
Date of Publication: 30 September 2004

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