Hardware prototyping for the H.264 4/spl times/4 transformation [video coding]

This paper presents a hardware prototype of the H.264 transformation. The proposed architecture uses only add and shift operations to reduce the computational requirements for the 4/spl times/4 transform. The architecture is developed to be used in high-resolution applications such as high definition television (HDTV) and digital cinema. The developed architecture is prototyped and simulated using ModelSim 5.4/spl reg/. It is synthesized using Leonardo Spectrum/spl reg/. The results show that the architecture satisfies the real-time constraints required by different digital video applications.