Pipelining of digital filter structures for VLSI implementation

Two pipelining techniques for VLSI implementation are presented, namely the interleaving technique and the delay technique. The techniques are based on using Z-transform and block diagram manipulation. The merits of each technique are discussed and several examples are given to illustrate their use. The interleaving technique is shown to be applicable to all filter structures; however, it decreases the speedup of processing rate due to zero-interleaving of input and output sequences. The speedup can be improved by interleaving several sequences. The delay technique has a linear increase in speedup; however, it introduces latency and is not applicable to all filter structures, especially IIR (infinite impulse response) filters.<>