A CMOS stuck-open fault simulator

The authors present a SOP (stuck-open) fault simulator for CMOS combinational circuits which is based on the single SOP fault model and the gate-level model of the circuit. In the simulator, the transport delay model is used to consider the effect of hazards of the circuit. The basic approach of the simulation is that the fault simulator detects a SOP fault only if the faulty gate output is properly initialized considering gate delays. For simplicity, it is assumed that the circuits consist of only primitive logic gates such as AND, OR, NAND, NOR, and inverter. Experimental results on the SOP fault converges of various CMOS combinational circuits for random pattern testing are provided.<>