On hardware overhead in CMOS BIST designs

The hardware overhead in CMOS BIST (built-in self-testing) designs are investigated. Various BIST components are implemented using CMOS and hardware overheads are assessed in terms of the number of transistors. Since the hardware overhead for each component is represented with a simple formula, it is very easy to estimate the hardware overhead in the early design process. The implementation of three components (built-in logic block observer, signature analysis register, and pseudorandom pattern generator) is described in detail.<>