Thermal characterization of stacked-die packages

Thermal characterization for multi-chip packages is a complicated process. Unlike the single-chip package, for which thermal resistance like /spl Theta//sub JA/ can be easily defined and measured, the presence of multiple heat sources in multi-chip packages makes the definition of thermal resistance impossible. In addition, multiple chip temperature typically needs to be measured at various power level combinations. In this paper, we studied a simple way to derive those chip temperatures by using the thermal resistance data from the equivalent single-chip packages. Our study is based on a comprehensive thermal evaluation of multi-chip packages. These packages contain 2 thermal test dice in a stacked fashion. Test samples were exclusively built based on 4 popular packaging types. Junction temperatures and board temperatures under standard JEDEC environment were measured using the Electrical Method and were correlated with the finite element-based detailed models. Based on an idealization of the heat transfer process, we derived a set of simple equations for approximating the junction and the board temperatures of stacked die packages. The only major input these equations require is the thermal resistance values of the equivalent single-chip packages, which are in general available. Therefore, no additional tests or simulations will be needed. In terms of accuracy, the new equations yielded promising results in most test cases although performance degradation does appear at certain package and boundary condition combinations.