A new dynamic circuit design technique for high performance TSC checker implementations [totally self checking circuits]

The use of a fault model that handles transistor level faults like transistor stuck-open and transistor stuck-on is highly desirable in modern designs. Unfortunately, in the case of self-checking checkers, exploited for on-line testing, the requirements of using pairs of test vectors or special circuits for I/sub DDQ/ monitoring may not be applicable. A variation of the dynamic circuit design technique, which uses multiple clocks to construct three phase logic structures, is presented which is capable of covering the above fault models. The proposed technique results in checker designs that combine high operating frequency and reduced area requirements while are capable of satisfying the required self-checking and fault-secure properties. Two-rail code checker designs are presented to demonstrate the proposed technique.