The effects of on-chip and package decoupling capacitors and an efficient ASIC decoupling methodology

This paper presents an in-depth analysis of the effectiveness of on-chip and package decoupling capacitors in light of the interaction between chip-package resonance and the frequency content of switching sources, and suggests an approach for decoupling analysis in fast turn-around ASIC designs, achieving both simulation efficiency and accuracy. The analysis is based on accurate modeling of the on-chip and package power supply structures of ASIC flip-chip modules as distributed networks to provide precise understanding of switching noise mechanisms in distributed power supply structures in both the time and frequency domains. The simulation efficiency versus accuracy of two types of package models is discussed. The local effectiveness of on-chip and package decoupling capacitors is illustrated using detailed, frequency-domain impedance profiles of the on-chip and package power supply networks, demonstrating location-dependant responses that vary according to the local placement of decoupling capacitors. Based on the study, a methodology is presented for accurately determining the quantities and locations of on-chip decoupling capacitors required to limit on-chip transient power supply collapse to a pre-defined level.