Decimation filter design

Decimation filters' architecture for an integrated power-meter is presented in this paper. It is based on parallel processing techniques and inherent pipelining and offers advantages in high speed operation, low power consumption and low complexity for VLSI implementation. The design process consists of several steps, and a full design procedure from the high level coefficients calculation to the synthesis phase performed using SE tools of Cadendce design system is given here. Digital filters are realized using Alcatel CMOS 0.35 technology and its library elements.