E-beam inspection of dislocations: product monitoring and process change validation

The process complexity of today's SOC (system on a chip) technologies, mixing pure logic, SRAM and DRAM process poses a great challenge to achieve high WFT (Wafer Final Test) yield. The numerous device process steps and up to 9 metal levels leads to typical cycle times of the order of 3 months from start of process to WFT. Having effective methods for inline detection and tracking of defect mechanisms can greatly increase the cycles of learning available to optimize processes and improve yields. This paper describes the use of E-beam voltage contrast inspection to provide detection, tracking and inline monitoring of an electrically active device defect. In this study, a yield detractor has been identified through physical failure analysis in a specific circuit localized in an embedded memory array. Shallow dislocations were observed giving rise to shorts in a NFET device and were shown to be the root cause of the functional failures. As a consequence, an innovative early feedback system using E-beam voltage contrast inspection was put in place immediately after the first wired metal level. The capability of the E-beam inspection tool to detect dislocations and classify accurately the defects with iADC (in line Automatic Defect Classification) is a real breakthrough for the yield ramp of these products. WFT to E-beam inspection correlation, iADC performance fine tuned using confusion matrix and appropriate failure analysis were all completed to ensure reliability of the results. Thus, by enabling evaluation at the first metal level, the E-beam tool provides accurate information on this dislocation failure at least 4 weeks prior to WFT and as a result saved precious time in evaluating process changes to reduce this defect. This is especially important when the process improvements to resolve defect issues are early in the Front End of Line (FEOL) process operations. Moreover, when using voltage contrast methods coupled with pattern recognition, the indication of the target defect is very specific and the fails on the circuit of interest are classified independently of all other types of fails. In comparison, WFT needs thorough analysis to partition the various functional fail signatures before one can conclude the level of dislocations present on the wafer. As shown in this study, the dislocation density trends from E-beam inspections allowed us to rapidly and efficiently implement a number of process changes to mitigate the dislocation problem and to provide a reliable outlook for WFT yield improvement.