A single chip radio transceiver for 802.11a/b/g WLAN in 0.18/spl mu/ CMOS

This paper presents design and performance of a single chip CMOS radio covering the Wi-Fi 802.11 a(5GHz) and 802.11 b(2.4GHz), and a draft version of the 802.11 g(2.4 GHz OFDM/CCK) wireless standard. The radio is based on a configurable and digitally programmable transceiver architecture and adopts a frequency plan that: a) avoids use of external image reject filters and b) allows design of integrated low phase noise frequency synthesizer, as required by 54Mb/s 64-QAM modulation, while maintaining low power consumption. The resulting solution achieves maximum hardware share as mixers, PLLs and analog baseband chains are shared amongst the three standards. It was implemented in 0.18/spl mu/ CMOS technology with a die size of 12 mm/sup 2/ in a 48-pin package.