ADC performance limitations due to quantizer non-idealities

A low-voltage low-power CMOS Sigma-Delta Modulator (SDM) is presented. The influence of a dynamic latched comparator on the performance of the SDM are studied with the help of SPICE simulations. SPICE BSIM4 models are used to study the transient behaviour of the overall circuit. The latched comparator is devised to be used to detect very small differential signals in the presence of large common-mode signals. An 8-bit second-order Sigma-Delta Modulator is used to demonstrate the limitations and potential, solutions associated with the use of the latched comparator. The aim of this study is to use such an ADC in the CMOS imagers to be realized in a low-cost standard digital process technology. Another aim of this study is to utilize an identical design layout of the latched comparator to quantize the full-scale range of signals (LSB to MSB).