A novel SiC J-FET gate drive circuit for sparse matrix converter applications

Three-phase AC/AC sparse matrix converters (SMC) show a low realization effort and a low control complexity and are therefore of potential interest for industry applications. In this paper a novel gate drive circuit for a SiC J-FETs to be employed in an AII-SiC-SMC is proposed. The gate drive requirements of SiC J-FETs are clarified and the operating principle of the driver circuit is discussed and practically verified in a bridge leg topology. The experimental analysis shows significant advantages of the proposed system over known SiC J-FET driver circuits concerning switching delay time and switching losses.