VHDL-AMS modeling of a new PLL with an inverse sine phase detector (ISPD PLL)

For improving the performance of PLL, a sin/sup -1/(x) function generator has been substituted for a standard phase detector. The behavior of blocks have been modeled with VHDL-AMS at different abstraction levels and compared with experimental results. We point out that connections between the blocks may need some (impedance) adaptation and physical accurate models may not be absolutely necessary for an accurate simulation of the loop.