Efficient Digital System Design Methodology with SystemC Register Transfer Level Modeling

In this competitive industrial market, maximizing time compression for new product development and release is paramount to achieving and sustaining strategic position. Designing applications for complex integrated circuits (IC) composed of tens of millions of transistors is the norm. These systems are composed of complex hardware modules integrated to create a System-On-Chip (SoCs) design. In today’s technology, Register Transfer Level (RTL) digital system designs and associated modeling of complex ICs have been based on two prominent hardware description language (HDLs)s known as VHDL and Verilog. However, a new arising HDL language being integrated in the design of these complex system is known as SystemC. The authors will discuss the digital designs around SystemC.