A Cycle Reducing Synchronous Logic Simulation

Parallel logic simulation is an important method for verifying the correctness of complex VLSI system designs. Synchronous simulation technique has low overhead but has poor load balancing and frequent synchronization cost. We derive a performance evaluation formula for the synchronous simulation. The formula considers factors including load balancing, the ratio between computation and communication and number of simulation cycles. The formula reveals that for simulations with very fine computation granularity, the reduction in simulation cycles is one of the most important keys to improve the performance. We propose an optimistic synchronous algorithm that is targeted to reduce the number of synchronization steps. The experimental results on ISCAS89 and ISCAS85 circuits show that the proposed algorithm performs significantly better than synchronous simulation. For non-unit delay models, the proposed algorithm performs almost as good as unit delay models.