The effective buffer architecture for data link layer of PCI express

In this paper, we propose an efficient buffer management scheme to increase performance of the PCI express architecture. It is necessary for the several buffers such as replay buffer in virtual channel and traffic class buffers to implement the PCI express architecture. The proposed scheme merges the buffers into only one buffer and dynamically adjusts size of the replay buffer space and traffic class buffers space to effectively support the ordering requirements of the PCI express. The simulation result shows 30% performance improvement over the conventional scheme that uses separated buffers.