Ultralow-voltage RAM technology - current status and future trends

This paper reviews leakage current reduction circuits for ultralow-voltage DRAMs and SRAMs. First, it discusses general features of leakage currents (especially, gate tunnel current and subthreshold current), their detrimental effects on RAMs, and the current status of leakage-current reduction. Second, it summarizes useful concepts to reduce subthreshold currents that can even be applied to the active mode. Third, the advantages of RAMs over random logic gates with respect to reducing subthreshold currents are clarified, and the above concepts are applied to RAM cells and peripheral circuits to reduce standby as well as active current. Finally, a perspective is given with emphasis on needs for new devices and circuits to reduce active-mode leakage currents, and for high-speed simple non-volatile RAMs.