NBTI mechanism explored on the back gate bias for pMOSFETs

Negative bias temperature instability had been getting more attention with the scaling down of MOS transistor, accompanied by the thinning of gate oxide. In our experiment of 0.15/spl mu/m dual gate CMOS process, it is shown that surface hole concentration will have much impact on NBTI by means of Vsb application, no matter for devices of 2.6-nm or 6.5-nm oxide thickness. The NBTI enhancement at high Vsb is believed to be caused by the substrate hot hole injection, which leads to more interface state and positive charge generation, and thus makes NBTI worse. On the other hand, we expect better NBTI results under low gate electric field with Vsb applied, due to reduction of surface hole from Vsb.