An InGaAs/InP p-i-n-JFET OEIC with a wing-shaped p/sup +/-InP layer

A receiver optoelectronic integrated circuit (OEIC) structure with an InGaAs p-i-n photodiode, InGaAs self-aligned junction FETs and a bias resistor has been fabricated on a semi-insulating InP substrate. The fabrication processes are highly compatible between the photodiode and the JFET, and reduction in FET gate length is achieved using anisotropic selective etching and a two-step organometallic vapor phase epitaxy (OMVPE) growth schedule. The 80- mu m diameter p-i-n detector exhibits a leakage current of 2 nA and a capacitance of about 0.35 pF at -5 V bias voltage. Extrinsic transconductance and a gate-source capacitance of the JFET are typically 45 mS/mm and 4.0 pF/mm at 0 V, respectively. The maximum voltage gain of the preamplifier is 12.5 and the bandwidth of the p-i-n amplifier OEIC is expected to be about 1.2 GHz.<>