VLSI architectures for distributed smart cameras

This paper discusses the VLSI architecture for distributed smart camera systems. We first introduce the core algorithm of the smart camera systems and then compare two different approaches of implementing a single node smart camera system. We show that by using heterogeneous multiprocessors, we can achieve a 150 frames/sec processing speed with a small die area cost of 22.7 mm/sup 2/. This approach requires less than half die size compared to multiple VLIW processors approach. In addition, the issues related to distributed smart cameras such as task scheduling, inter-processor communication, and synchronization is discussed.