FET fabricated by layer-by-layer nanoassembly

Metal-oxide-semiconductor field-effect transistor (MOSFET) arrays are fabricated on a 4-in silicon wafer by the combination of conventional microelectronic processes and layer-by-layer nanofabrication. The active and insulating layers were self-assembled as organized multilayers of 15-nm diameter SnO/sub 2/ and 45-nm diameter SiO/sub 2/ nanoparticles, respectively. The source, drain, and gate electrodes are made of metal thin films. The threshold voltage is 3 V, on-off current ratio 10/sup 4/, and mobility 2.1/spl times/10/sup -2/ cm/sup 2//V/spl middot/s. This prototype leads to a new approach to fabricate low-cost MOSFETs and integrated circuits based on the layer-by-layer self-assembly of nanoparticles and charged macromolecules.