Estimating pre-placement FPGA interconnection requirements

With increasing device and design sizes, Interconnect Planning is fast becoming an important design issue for large FPGA based designs. The fundamental requirement for interconnect planning is the ability to estimate the routing requirements of a given design at all stages of physical design. A number of interconnect estimation methods have been proposed, but very few operate prior to placement. Pre-placement estimation is very useful for detailed design space exploration during logic synthesis and earlier stages of design. We propose a new local neighborhood analysis based method to estimate the wirelengths of every net in a given netlist, prior to placement. We assume an optimal placement with respect to total wirelength and estimate the bounding-box sizes of all the nets. We then use the bounding-box estimates to compute the post-routing peak channel width of the device. Our method efficiently handles pad constrained designs. We compare our net bounding-box and peak channel width estimates with the post-placement and post-routing results obtained using VPR, a commonly used FPGA tool suite.