Low power combinational circuit synthesis targeting multiplexer based FPGAs

Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. Technology decomposition schemes often ignore the fact that certain circuit elements can be mapped more efficiently by treating them separately during decomposition. Multiplexers are one such category of circuit elements. Mapping them using multiplexers in technology libraries has many advantages. The aim of this work is to exploit the potential of the multiplexers and decompose a combinational circuit targeting a reduction in the power consumption by the circuit. A technology mapping of this decomposed circuit onto the Actel's FPGA architecture, further reducing the power consumption, is also presented. The experimental results show on an average of over 55% reduction in power consumption over the SIS approach.