Implications of halo and well implant conditions on sub-140nm device technologies

With the increase in device complexity, the drive for higher performance and yield, to improve lab profitability, has led to tighter requirements for uniformity and repeatability of the ion implant steps. In particular, implants such as the Halo and well, where the device parametrics, e.g. threshold voltage (VI), leakage current and breakdown voltage are strongly affected. In this paper, a TCAD sensitivity study of Halo implant angle effect on V_t has been conducted and verified on PMOS devices. Device wafer splits were also conducted on the effect of well and Halo implants. Parametrics of N well implant splits will be presented.