Inductor-less, 10Gb/s limiter with 10mV sensitivity and offset/temperature compensation in baseline CMOS18

The paper presents an inductor-less 10Gb/s limiting amplifier with offset and temperature compensation for high-speed data communications realized in a baseline CMOS process. For achieving the sensitivity required in long-haul applications (SONET/SDH) a new technique described as slew-boosting is introduced. A balanced integrator circuit amplifies the offset from the output and feeds back a correct signal at the input for the offset compensation. The limiter has been implemented in the standard CMOS18 process. The measured sensitivity of the circuit is 10mV@10GB/s. The circuit can work up to 12Gb/s with reduced performance. At 10Gb/s and 10 mV input, the output amplitude is 300mV with 2.5ps jitter-rms and rise/fall times of 17 ps. The active area of the circuit without bonding pads is 0.8/spl times/0.5mm/sup 2/ and the power consumption is 144mW from a 1.8V supply voltage at room temperature.