Micro-network for SoC: implementation of a 32-port SPIN network

We present a physical implementation of a 32-ports SPIN (scalable programmable integrated network) micro-network. For a 0.13 /spl mu/m CMOS process, the total area is 4.6 mm/sup 2/, for a cumulated bandwidth of about 100 Gbits/s. In a 6 metal process, all the routing wires can be routed on top of the switching components. The SPIN32 macro-cell will be fabricated by ST Microelectronics, but this macrocell uses a symbolic layout, and can be manufactured with any CMOS process including 6 metal layers.