A deterministic globally asynchronous locally synchronous microprocessor architecture

We describe a novel globally-asynchronous locally-synchronous (GALS) architecture called "synchro-tokens" which exhibits deterministic state and output sequences. This deterministic behavior facilitates industrial validation, debug, and test methodologies which rely on predictable and repeatable system behavior. The synchro-tokens architecture uses token rings for handshaking and self-timed FIFOs for pipelined interconnect. Local counters keep track of how long a token is held and the elapsed time since it was last released to ignore early tokens and to stop the local clock to wait for late tokens. Because no synchronizers are used, there is zero probability of failure due to metastability. Architectural parameters, such as FIFO sizes, counter values, and clock frequencies, offer a great deal of flexibility for tuning the system performance.