A fully-integrated 10.5 to 13.5 Gbps transceiver in 0.13 /spl mu/m CMOS

The design of a fully-integrated 10.5 to 13.5 Gbps transceiver is presented. The chip uses a half-rate architecture for both the transmitter and receiver. Duo-binary and electrical RZ pre-coding are implemented in the transmitter. The receiver uses a high-gain input buffer with a new digital offset cancellation technique to achieve 15 mVpp differential input sensitivity. Programmable phase tuning capability in the clock and data recovery (CDR) loop provides optimum data sampling instants. The transceiver occupies 8 mm/sup 2/ and dissipates 1 W in a 0.13 /spl mu/m digital CMOS process.