The WASP 2 WSI massively parallel processor demonstrators

WASP 1 is reviewed, and the WASP 2a and WASP 2b wafer-scale integration (WSI) massively parallel processor technology demonstrators, implemented in standard CMOS technology, are discussed. These latter devices are defect-tolerant arrays of 864 and 6048 processing elements and integrate 1.26 M transistors (4 cm*4 cm) and 7.87 M transistors (10 cm*10 cm). The two variants (WASP 2a and WASP 2b) are examples of the associative string processor (ASP) architecture, developed at Brunel University. WASP 2a/2b, as well as their successful predecessor, WASP 1, are the technology demonstrators of the UK Alvey WSI program.<>