Building-cell design methodology for high-speed GaAs standard-cell LSIs

A novel layout concept of Building-Cell (BC) methodology which realizes high-speed GaAs standard-cell LSIs is introduced. This methodology reduces the layout area and wiring-length, and leads to a large degree of freedom for cell placement. A GaAs data bus LSI, consisting of 3500 gates and a 75-bit register file, was designed to verify the effectiveness of this methodology, which functioned at a fast cycle time of 7 ns.<>